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shahbaaz lokhandwala

How to create MAXI interface with address offset = off

Advanced extensible Interface(AXI) is an on chip bus communication protocol developed by ARM [https://www.arm.com/]. This blog post is about creating a custom IP with one MAXI (Master-AXI) port. One MAXI port can communicate with one or multiple Slave-AXI ports of other IPs. Generally on FPGAs, it

How to create MAXI interface with address offset = slave

Advanced extensible Interface (AXI) is an on-chip bus communication protocol developed by ARM [https://www.arm.com/]. This blog post is about creating a custom IP with one MAXI (Master-AXI) port. One MAXI port can communicate with one or multiple Slave-AXI ports of other IPs. Generally on FPGAs, it is

Using XDMA PCIE with DDR MEMORY in Vivado

Using XDMA PCIE with DDR MEMORY in Vivado

Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board Nitefury is a M.2 form factor FPGA development board that has Artix-7 FPGA with onboard DDR3 memory. It can be connected to a laptop or motherboard that has M.2 pcie connector or that

Top 10 FPGA Companies

Top 10 FPGA Companies

Over time, FPGAs have become key in all kinds of industries, from Semiconductors to Military operations and more advanced technologies, like Artificial Intelligence. Since their invention, two major companies have been leading the market: Xilinx and Altera (acquired by Intel in 2015, but these are not the only FPGA vendors