Our Recent Work

Algorithm-Intensive Projects:

RTL Design of SHA3 512/256 (also known as Keccak algorithm)

• Created to offer you a hash with clock cycles running at speeds of 550MHz
• Tested on the Xilinx Virtex UltraScale+ FPGA BCU1525 Acceleration Development Kit
• Connected with PCIe Interface Host
• Benchmarked on mining pools with 17GH/s
  

RTL Design of SHA-256 (aka Bitcoin algorithm)

• Designed to give you a hash at every single clock cycle running at 350MHz
• Tested on the BCU1525 Acceleration Development Kit with PCIe Interface Host
  

RTL Design of Keccak 800 (aka Odocrypt algorithm)

• Designed to give you a hash at every single clock cycle running at 300MHz
• Tested on the BCU1525 Acceleration Development Kit
• Optimized for throughput
  

RTL Design of Ethereum algorithm

• Designed to work on FK33 board running at 400MHz
• Designed custom MAXI bus interface to communicate with HBM memory

If you need help with your project, you can review our FPGA design services for a better understanding of the services we offer.